The present invention is generally directed to the formation of via openings in large scale integrated circuit devices. More particularly, the present invention is directed to the use of aluminum oxide as an etch stop material.
In the fabrication of very large scale integrated circuit devices (VLSI), it is desirable to shrink feature sizes as much as possible, and preferably to sizes smaller than one micron. This shrinking in device size enables circuit chip designers to incorporate many more electrical circuit and logic functions on a single device. Shrinkage of device dimensions also increases the speed at which the devices can operate since propagation delay between distinct devices is reduced along with reduction in the distance between adjacent devices.
However, the shrinkage of device sizes is fraught with many practical problems. In particular, because of registration problems encountered with the use of different photo masks used in device patterning, it is typically necessary to employ "frames" around via openings which extend between different layers in VLSI devices. These frames are typically present as wider areas in the metal interconnection patterns. They are provided to ensure contact between upper and lower levels of metallization through via openings in a dielectric layer in spite of mask alignment or registration variations. However, via frames not only consume device area, but also increase the distance between metallization line patterns (line pitch). The via frames are required to be sufficiently large to ensure interlevel electrical connection even in the case of mask misalignment or misregistration. The size of the via frames then is seen to be a limiting factor in shrinking overall device size.
Prior attempts at developing unframed via connections to increase interconnection layout density have generally formed a via opening by etching down to an unframed metal line buried in a material such as silicon oxide. Since the depth of the required via depends on which layer is being contacted and since the depth of any given layer at various locations is usually different after planarization of overlying dielectric layers, many via depths must be etched in the same step. Furthermore, in unframed structures, vias are not always precisely aligned with underlying conductors resulting in an etch which often etches beyond the edge of these underlying conductors. This often further contributes to poor interlevel connections. Moreover, the selectivity of nitride or oxy-nitride used as an etch stop is not sufficiently high to effectively block the over-etching.